Micron has mapped out a multi-year plan for memory and storage, linking future DDR6, LPDDR6, HBM and NAND parts to a process node that is due for mass manufacturing in the second half of 2027. The node is named 1-Delta, and Micron expects it to support products from server modules that can hold a terabyte to flash chips with more than 400 layers. The disclosure comes as spending on AI infrastructure keeps driving hardware prices upward.
- Key Point: Micron says 1-Delta will raise bit density by roughly 25% over 1-Gamma when used to build advanced DRAM.
- Key Point: DDR6 is pitched at AI data-center servers, should offer more than twice DDR5 bandwidth, and has no announced launch date.
- Key Point: Micron is targeting 1TB RDIMMs for dense AI workloads and says they will be the largest-capacity modules of their kind once in production.
- Key Point: G11 NAND, with over 400 layers, aims for double G9 bit density, 1.5x I/O speed and at least 25% less energy per transfer.
1-Delta process and future DRAM designs
1-Delta follows 1-Gamma. Micron says the newer node combines angstrom-level process control with an HKMG CMOS structure, producing about a quarter more bit density than the earlier generation in advanced DRAM. The company also said later memory products will move to 6F² DRAM cells rather than 4F². It pointed to cost, complexity and capacitor pitch limits that sharply cap how far 4F² can scale.
Further ahead, Micron expects next-generation DRAM to use wafer bonding and High-NA EUV, with the possibility of newer materials after that. It is also developing 3D DRAM as a longer-term option.
Server-first DDR6 and one-terabyte modules
1-Delta is set to support standards such as DDR6 and LPDDR6. Micron says DDR6 can deliver more than double DDR5 bandwidth, but it is not presenting the standard as a simple replacement for client-PC memory. Instead, the company frames it as dependable server memory aimed at AI data centers. No official DDR6 launch date has been set.
In September 2026, Micron showed a DDR5 RDIMM of 512GB capacity that ran at 9,200MT/s. It now says its next generation will yield one-terabyte RDIMMs aimed at AI workloads that need high density, and claims that, when production begins, these will be the industry’s highest-capacity RDIMMs.
Low-power memory, stacked HBM and G11 flash
For low-power memory, Micron claims LPDDR6 will be 35% more power-efficient than LPDDR5, with larger gains at some densities. Scott DeBoer, who holds Micron’s president title and also serves as chief technology and products officer, said the company is cooperating with several partners, Meta among them, to place LPDDR6 in AI data centers.
Micron is working with a range of partners, including Meta, to deploy LPDDR6 memory in AI data centers.
Micron also unveiled vHBM, a vertical stacking design that places memory directly above the compute die. According to the company, this raises bandwidth per watt in its upcoming HBM chips. On storage, Micron described G11 NAND, a flash chip family featuring over 400 layers. Against G9, it targets double the bit density, 1.5x I/O throughput and a reduction of more than 25% in energy per transfer. G11 is also due to enter production in the second half of 2027, though Micron has not announced a launch date.
The common thread is timing. 1-Delta, the 1TB RDIMMs and G11 all converge on the same second-half 2027 window, leaving several quarters before any of this silicon reaches the market. For buyers, the roadmap stresses capacity and efficiency rather than lower prices: the same AI build-out that creates demand for terabyte-class RDIMMs is also the pressure Micron cites behind rising hardware costs. Whether DDR6 stays server-only or eventually reaches client PCs will depend on how quickly data-center demand absorbs early supply.